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andreagallo-dev/README.md

Hi there, I'm Andrea 👋

I'm an Aspiring Automation Engineer with a passion for the hardware-software interface, Robotics, Homelabbing, RISC-V architecture, FPGA design. I am currently a Dual Degree student at the University of Bologna and Tongji University, Shanghai.

🔭 I’m currently working on:

  • Refining my 5-stage pipelined RISC-V processor.
  • Exploring embedded graphics with custom SoC peripherals.
  • Developing and simulating mobile robot navigation and control systems using ROS2 and Gazebo.

🌱 I’m currently learning:

  • Advanced verification techniques for complex digital systems.
  • Mobile robotics tools.

📫 How to reach me:

⚡ My Key Projects:

Pinned Loading

  1. risc-v-pipelined-processor-by-Gallo-Andrea risc-v-pipelined-processor-by-Gallo-Andrea Public

    A 5-stage pipelined processor compliant with the RISC-V RV32I ISA, featuring full hazard detection and resolution.

    SystemVerilog 1

  2. fpga-automotive-taillight-controller fpga-automotive-taillight-controller Public

    An FSM-controlled automotive tail light system in Verilog for a Xilinx Artix-7 FPGA, featuring a unique emergency mode with a real-time 7-segment display timer.

    Verilog 1

  3. riscv-soc-hdmi-controller riscv-soc-hdmi-controller Public

    A custom graphics peripheral in Verilog for a RISC-V SoC, featuring an ICB bus interface and controlled by C firmware to render ASCII text on an HDMI display.

    Verilog 2

  4. a-2009-server-odyssey a-2009-server-odyssey Public

    A high-efficiency home server build based on OpenMediaVault 7, optimized for 2009-era legacy hardware with limited resources

    Shell

  5. Cinnamon_Linux-rice Cinnamon_Linux-rice Public

    My first linux rice, created for Cinnamon DE (used Mint as OS)

    CSS 6